This invention relates to metal oxide semiconductor (MOS) random access memories (RAMS) in which the memory cell has a single MOS transistor and a single capacitor connected in series and having twice the sensed signal of conventional arrangements.
In the usual MOS RAM utilizing a single capacitor and a single MOS transistor in a memory cell, one side of the capacitor, the side referred to as the field plate, is conventionally connected directly to the power line, and the sensing is accomplished by charging and discharging of the capacitor on the opposite side through a switch driven by the word line into a bit line that is precharged to a certain voltge level. The small change in the bit line voltage due to charging and discharging of the capacitor is sensed in a sense amplifier against a reference signal. The reference signal is roughly one half the value of the cell signal caused by the charge and discharge of the cell capacitor, so the sensed signal is one half of the cell signal.